/**
 *******************************************************************************
 * @file  hc32f160_interrupts.c
 * @brief This file provides firmware functions to manage the Interrupt Controller
 *        (INTC).
 @verbatim
   Change Logs:
   Date             Author          Notes
   2020-11-27       CDT             First version
 @endverbatim
 *******************************************************************************
 * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
 *
 * This software component is licensed by HDSC under BSD 3-Clause license
 * (the "License"); You may not use this file except in compliance with the
 * License. You may obtain a copy of the License at:
 *                    opensource.org/licenses/BSD-3-Clause
 *
 *******************************************************************************
 */

/*******************************************************************************
 * Include files
 ******************************************************************************/
#include "hc32f160_interrupts.h"
#include "hc32f160_utility.h"

/**
 * @addtogroup HC32F160_DDL_Driver
 * @{
 */

/**
 * @defgroup DDL_INTERRUPTS INTERRUPTS
 * @brief INTC Driver Library
 * @{
 */

#if (DDL_INTERRUPTS_ENABLE == DDL_ON) || (DDL_EXTINT_NMI_ENABLE == DDL_ON) ||   \
    (DDL_EKEY_ENABLE == DDL_ON)

/*******************************************************************************
 * Local type definitions ('typedef')
 ******************************************************************************/

/*******************************************************************************
 * Local pre-processor symbols/macros ('#define')
 ******************************************************************************/
/**
 * @defgroup INTC_Local_Macros INTC Local Macros
 * @{
 */
/**
 * @brief   Maximum IRQ handler number
 */
#define IRQ_NUM_MAX         (16U)

/**
 * @brief Wakeup event enable mask
 */
#define INTC_WUPEN_MASK                                                         \
            (INTC_WUPENR_EIRQWUEN   | INTC_WUPENR_RTCPRDWUEN        |           \
             INTC_WUPENR_RTCALMWUEN | INTC_WUPENR_PVDWUEN           |           \
             INTC_WUPENR_TMR0CMPWUEN| INTC_WUPENR_EKEYWUEN          |           \
             INTC_WUPENR_SWDTWUEN)

/**
 * @brief Event enable mask
 */
#define INTC_EVT_MASK                                                           \
            (INTC_EVTER_EVTEN0      | INTC_EVTER_EVTEN1             |           \
             INTC_EVTER_EVTEN2      | INTC_EVTER_EVTEN3             |           \
             INTC_EVTER_EVTEN4      | INTC_EVTER_EVTEN5             |           \
             INTC_EVTER_EVTEN6      | INTC_EVTER_EVTEN7)

/**
 * @defgroup INTC_Check_Parameters_Validity INTC Check Parameters Validity
 * @{
 */
/*  Parameter validity check for wakeup source from stop mode. */
#define IS_INTC_WKUP_SRC(src)                                                   \
(   ((src) != 0x00UL)                           &&                              \
    (((src) | INTC_WUPEN_MASK) == INTC_WUPEN_MASK))

/*  Parameter validity check for event number. */
#define IS_INTC_EVT(evt)                                                        \
(   ((evt) != 0x00UL)                           &&                              \
    (((evt) | INTC_EVT_MASK) == INTC_EVT_MASK))

/*  Parameter validity check for NMI trigger souce. */
#define IS_NMI_SRC(src) (((src) & NMI_SRC_MASK) != (uint8_t)0x00u)

/*  Parameter validity check for get NMI trigger source. */
#define IS_GET_NMI_SRC(src)                                                     \
(   ((src) == NMI_SRC_XTAL_STP)                 ||                              \
    ((src) == NMI_SRC_SWDT)                     ||                              \
    ((src) == NMI_SRC_LVD))

/*  Parameter validity check for EXTINT filter function. */
#define IS_EXTINT_FE(fe)                                                        \
(   ((fe) == EXTINT_FILTER_OFF)                 ||                              \
    ((fe) == EXTINT_FILTER_ON))

/*  Parameter validity check for EXTINT filter clock division. */
#define IS_EXTINT_FCLK(fclk)                                                    \
(   ((fclk) == EXTINT_FILTER_CLK_DIV1)          ||                              \
    ((fclk) == EXTINT_FILTER_CLK_DIV8)          ||                              \
    ((fclk) == EXTINT_FILTER_CLK_DIV32)         ||                              \
    ((fclk) == EXTINT_FILTER_CLK_DIV64))

/*  Parameter validity check for EXTINT trigger edge. */
#define IS_EXTINT_TRIG(trigger)                                                 \
(   ((trigger) == EXTINT_TRIG_LOW)              ||                              \
    ((trigger) == EXTINT_TRIG_RISING)           ||                              \
    ((trigger) == EXTINT_TRIG_FALLING)          ||                              \
    ((trigger) == EXTINT_TRIG_BOTH))

/*  Parameter validity check for EXTINT channel. */
#define IS_EXTINT_CH(ch)     (((ch) & EXTINT_CH_MASK) != (uint16_t)0x0000u)

/*  Parameter validity check for get EXTINT channel. */
#define IS_GET_EXTINT_CH(ch)                                                    \
(   ((ch) == EXTINT_CH00)                       ||                              \
    ((ch) == EXTINT_CH01)                       ||                              \
    ((ch) == EXTINT_CH02)                       ||                              \
    ((ch) == EXTINT_CH03)                       ||                              \
    ((ch) == EXTINT_CH04)                       ||                              \
    ((ch) == EXTINT_CH05)                       ||                              \
    ((ch) == EXTINT_CH06)                       ||                              \
    ((ch) == EXTINT_CH07)                       ||                              \
    ((ch) == EXTINT_CH08)                       ||                              \
    ((ch) == EXTINT_CH09))

/*  Parameter validity check for EKEY. */
#define IS_INTC_EKEY(ekey)  (((ekey) & EKEY_CH_MASK) != (uint8_t)0x00u)

/* Parameter validity check for GPIO register lock status. */
#define IS_INTC_UNLOCK()            (INTC_REG_UNPROTECT == (CM_INTC->FPRCR))

/**
 * @}
 */

/**
 * @}
 */

/*******************************************************************************
 * Global variable definitions (declared in header file with 'extern')
 ******************************************************************************/

/*******************************************************************************
 * Local function prototypes ('static')
 ******************************************************************************/
/**
 * @defgroup INTC_Local_Variable INTC Local Variable
 * @{
 */
static func_ptr_t m_apfnIrqHandler[IRQ_NUM_MAX] = {NULL};
static func_ptr_t m_pfnNmiCallback;
/**
 * @}
 */

/*******************************************************************************
 * Local variable definitions ('static')
 ******************************************************************************/

/*******************************************************************************
 * Function implementation - global ('extern') and local ('static')
 ******************************************************************************/
/**
 * @defgroup INTC_Global_Functions INTC Global Functions
 * @{
 */
/**
 * @brief  IRQ registration function
 * @param  [in] pstcIrqSignConfig: pointer of IRQ registration structure
 *   @arg  enIntSrc: can be any value except INT_PORT_EIRQ0~7 @ref en_int_src_t
 *   @arg  enIRQn: can be any value from INT008~INT023 @ref IRQn_Type
 *   @arg  pfnCallback: Callback function
 * @retval Ok: IRQ register successfully
 *         ErrorInvalidParameter: IRQ No. and Peripheral Int source are not match;
 *                                Input peripheral Int source cannot be configure;
 *                                NULL pointer.
 */
en_result_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig)
{
    __IO uint32_t *ISELRx;
    en_result_t enRet = Ok;

    /* Check if pointer is NULL */
    if (NULL == pstcIrqSignConfig)
    {
        enRet = ErrorInvalidParameter;
    }
    else
    {
        /* Checking validity for Interrupt source of Group 0~7 and IRQ No. */
        if ((((uint32_t)pstcIrqSignConfig->enIntSrc / 0x10U)*2U + 8U != (uint32_t)pstcIrqSignConfig->enIRQn) && \
            (((uint32_t)pstcIrqSignConfig->enIntSrc / 0x10U)*2U + 9U != (uint32_t)pstcIrqSignConfig->enIRQn))
        {
            enRet = ErrorInvalidParameter;
        }
        else
        {
            /* EIRQ0~7 are fixed allocation of IRQ handler 0~7 */
            if ((0u == (uint32_t)pstcIrqSignConfig->enIntSrc % 0x10U) || ((uint32_t)pstcIrqSignConfig->enIRQn < 8U))
            {
                enRet = ErrorInvalidParameter;
            }
            else
            {
                DDL_ASSERT(IS_INTC_UNLOCK());

                ISELRx = (__IO uint32_t *)((uint32_t)(&CM_INTC->ISELAR8) +      \
                                                     (4U * ((uint32_t)pstcIrqSignConfig->enIRQn - 8U)));
                *ISELRx = ((uint32_t)pstcIrqSignConfig->enIntSrc) % 0x10U;

                /* Callback function */
                m_apfnIrqHandler[(uint32_t)pstcIrqSignConfig->enIRQn - 8U] = pstcIrqSignConfig->pfnCallback;
            }
        }
    }
    return enRet;
}

/**
 * @brief  IRQ sign out function
 * @param  [in] enIRQn: can be any value from INT008_IRQn ~ INT023_IRQn @ref IRQn_Type
 * @retval Ok: IRQ sign out successfully
 *         ErrorInvalidParameter: IRQ No. is out of range
 */
en_result_t INTC_IrqSignOut(IRQn_Type enIRQn)
{
    __IO uint32_t *ISELRx;
    en_result_t enRet = Ok;

    if ((enIRQn < INT008_IRQn) || (enIRQn > INT023_IRQn))
    {
        enRet = ErrorInvalidParameter;
    }
    else
    {
        ISELRx = (__IO uint32_t *)((uint32_t)(&CM_INTC->ISELAR8) +    \
                                                     (4U * ((uint32_t)enIRQn - 8U)));
        WRITE_REG32(*ISELRx, 0x00UL);
        m_apfnIrqHandler[(uint32_t)enIRQn - 8U] = NULL;
    }
    return enRet;
}

/**
 * @brief  Share IRQ configure
 * @param  [in] enIntSrc: Peripheral interrupt source @ref en_int_src_t
 * @param  [in] enNewState:
 *   @arg  Enable: Enable corresponding peripheral interrupt in share IRQ handler
 *   @arg  Disable: Disable corresponding peripheral interrupt in share IRQ handler
 * @retval Ok: Share IRQ configure successfully
 *         ErrorInvalidParameter: EXTINT00~07 cannot be configured into share IRQ handler
 */
en_result_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState)
{
    __IO uint32_t *ISELRx;
    en_result_t enRet = Ok;

    /* EXTINT0~7 cannot be configured into share IRQ */
    if (0U == (uint32_t)enIntSrc % 0x10U)
    {
        enRet = ErrorInvalidParameter;
    }
    else
    {
        DDL_ASSERT(IS_INTC_UNLOCK());

        ISELRx = (__IO uint32_t *)(((uint32_t)&CM_INTC->ISELBR24) + (4U * ((uint32_t)enIntSrc / 0x10U)));
        if (Enable == enNewState)
        {
            SET_REG32_BIT(*ISELRx, (1UL << ((uint32_t)enIntSrc % 0x10U)));
        }
        else
        {
            CLEAR_REG32_BIT(*ISELRx, (1UL << ((uint32_t)enIntSrc % 0x10UL)));//todo confirm u or ul
        }
    }
    return enRet;
}

/**
 * @brief  Stop mode wake-up source configure
 * @param  [in] u32WakeupSrc: Wake-up source
 *   @arg  INTC_WUPENR_EIRQWUEN
 *   @arg  INTC_WUPENR_EIRQWUEN
 *   @arg  INTC_WUPENR_EIRQWUEN_0
 *   @arg  INTC_WUPENR_EIRQWUEN_1
 *   @arg  INTC_WUPENR_EIRQWUEN_2
 *   @arg  INTC_WUPENR_EIRQWUEN_3
 *   @arg  INTC_WUPENR_EIRQWUEN_4
 *   @arg  INTC_WUPENR_EIRQWUEN_5
 *   @arg  INTC_WUPENR_EIRQWUEN_6
 *   @arg  INTC_WUPENR_EIRQWUEN_7
 *   @arg  INTC_WUPENR_EIRQWUEN_8
 *   @arg  INTC_WUPENR_EIRQWUEN_9
 *   @arg  INTC_WUPENR_EIRQWUEN_10
 *   @arg  INTC_WUPENR_EIRQWUEN_11
 *   @arg  INTC_WUPENR_SWDTWUEN
 *   @arg  INTC_WUPENR_EKEYWUEN
 *   @arg  INTC_WUPENR_TMR0CMPWUEN
 *   @arg  INTC_WUPENR_PVDWUEN
 *   @arg  INTC_WUPENR_RTCALMWUEN
 *   @arg  INTC_WUPENR_RTCPRDWUEN
 * @param  [in] enNewState
 *   @arg  Enable: Enable corresponding wake up source
 *   @arg  Disable: Disable corresponding wake up source
 * @retval None
 */
void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState)
{
    /* Parameter validity checking */
    DDL_ASSERT(IS_INTC_WKUP_SRC(u32WakeupSrc));
    DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
    DDL_ASSERT(IS_INTC_UNLOCK());

    if (Enable == enNewState)
    {
        SET_REG32_BIT(CM_INTC->WUPENR, u32WakeupSrc);
    }
    else
    {
        CLEAR_REG32_BIT(CM_INTC->WUPENR, u32WakeupSrc);
    }
}

/**
 * @brief  Event or Interrupt output configure
 * @param  [in] u32Event: Event index
 *   @arg  INTC_EVTER_EVTEN0
 *   @arg  INTC_EVTER_EVTEN1
 *   @arg  INTC_EVTER_EVTEN2
 *   @arg  INTC_EVTER_EVTEN3
 *   @arg  INTC_EVTER_EVTEN4
 *   @arg  INTC_EVTER_EVTEN5
 *   @arg  INTC_EVTER_EVTEN6
 *   @arg  INTC_EVTER_EVTEN7
 * @param  [in] enNewState
 *   @arg  Enable: Enable corresponding event to NVIC
 *   @arg  Disable: Disable corresponding event but interrupt to NVIC
 * @retval None
 */
void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState)
{
    /* Parameter validity checking */
    DDL_ASSERT(IS_INTC_EVT(u32Event));
    DDL_ASSERT(IS_INTC_UNLOCK());

    if (Enable == enNewState)
    {
        SET_REG32_BIT(CM_INTC->EVTER, u32Event);
    }
    else
    {
        CLEAR_REG32_BIT(CM_INTC->EVTER, u32Event);
    }
}

/**
 * @brief  Initialize NMI. Fill each pstcNmiInit with default value
 * @param  [in] pstcNmiInit: Pointer to a stc_nmi_config_t structure that
 *                             contains configuration information.
 * @retval Ok: NMI structure initialize successful
 *         ErrorInvalidParameter: NULL pointer
 */
en_result_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit)
{
    en_result_t enRet = Ok;

    /* Check if pointer is NULL */
    if (NULL == pstcNmiInit)
    {
        enRet = ErrorInvalidParameter;
    }
    else
    {
        /* Configure to default value */
        pstcNmiInit->u32NmiSrc        = 0U;
        pstcNmiInit->pfnNmiCallback   = NULL;
    }
    return enRet;
}

/**
 * @brief  Initialize NMI.
 * @param  [in] pstcNmiInit: Pointer to a pstcNmiInit structure that
 *                             contains configuration information.
 * @retval Ok: NMI initialize successful
 *         ErrorInvalidParameter: NULL pointer
 */
en_result_t NMI_Init(const stc_nmi_init_t *pstcNmiInit)
{
    en_result_t enRet = Ok;

    /* Check if pointer is NULL */
    if ((NULL == pstcNmiInit) || (NULL == pstcNmiInit->pfnNmiCallback))
    {
        enRet = ErrorInvalidParameter;
    }
    else
    {
        /* Parameter validity checking */
        DDL_ASSERT(IS_NMI_SRC(pstcNmiInit->u32NmiSrc));
        DDL_ASSERT(IS_INTC_UNLOCK());

        /* Clear all NMI trigger source before set */
        WRITE_REG8(CM_INTC->NMICLR, INTC_NMICLR_MASK);

        /* NMI trigger source configure */
        WRITE_REG8(CM_INTC->NMIER, pstcNmiInit->u32NmiSrc);

        /* NMI callback function configure */
        m_pfnNmiCallback = pstcNmiInit->pfnNmiCallback;
    }
    return enRet;
}

/**
 * @brief  Get NMI trigger source
 * @param  [in] u32Flag: NMI trigger source, @ref NMI_TriggerSrc_Sel for details
 *   @arg  NMI_SRC_XTAL_STOP
 *   @arg  NMI_SRC_SWDT
 *   @arg  NMI_SRC_LVD
 * @retval Set: NMI is triggered by corresponding source
 *         Reset: NMI is not triggered by corresponding source
 */
en_flag_status_t NMI_GetNmiStatus(uint32_t u32Flag)
{
    /* Parameter validity checking */
    DDL_ASSERT(IS_NMI_SRC(u32Flag));

    return (0UL != (READ_REG32(CM_INTC->NMIFR) & u32Flag)) ? Set : Reset;
}

/**
 * @brief  Clear specified NMI trigger source
 * @param  [in] u32Flag: NMI trigger source, @ref NMI_TriggerSrc_Sel for details
 *   @arg  NMI_SRC_XTAL_STOP
 *   @arg  NMI_SRC_SWDT
 *   @arg  NMI_SRC_LVD
 * @retval None
 */
void NMI_ClearNmiStatus(uint32_t u32Flag)
{
    /* Parameter validity checking */
    DDL_ASSERT(IS_NMI_SRC(u32Flag));
    DDL_ASSERT(IS_INTC_UNLOCK());

    MODIFY_REG32(CM_INTC->NMICLR, INTC_NMICLR_MASK, u32Flag);
}

/**
 * @brief  NMI IRQ handler
 * @param  None
 * @retval None
 */
void NMI_IrqHandler(void)
{
    if (NULL != m_pfnNmiCallback)
    {
        m_pfnNmiCallback();
    }
}

/**
 * @brief  Initialize External interrupt.
 * @param  [in] u32Ch Channel of external interrupt
 *   @arg  EXTINT_CH00
 *   @arg  EXTINT_CH01
 *   @arg  EXTINT_CH02
 *   @arg  EXTINT_CH03
 *   @arg  EXTINT_CH04
 *   @arg  EXTINT_CH05
 *   @arg  EXTINT_CH06
 *   @arg  EXTINT_CH07
 *   @arg  EXTINT_CH08
 *   @arg  EXTINT_CH09
 *   @arg  EXTINT_CH10
 *   @arg  EXTINT_CH11
 * @param  [in] pstcExtIntInit: Pointer to a pstcExtIntInit structure that
 *                             contains configuration information.
 * @retval Ok:  EXTINT initialize successful
 *         ErrorInvalidParameter: NULL pointer
 */
en_result_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit)
{
    uint32_t u32ExtIntPos;
    en_result_t enRet = Ok;

    /* Check if pointer is NULL */
    if (NULL == pstcExtIntInit)
    {
        enRet = ErrorInvalidParameter;
    }
    else
    {
        /* Parameter validity checking */
        DDL_ASSERT(IS_EXTINT_FE(pstcExtIntInit->u32ExtIntFilter));
        DDL_ASSERT(IS_EXTINT_FCLK(pstcExtIntInit->u32ExtIntFilterClock));
        DDL_ASSERT(IS_EXTINT_TRIG(pstcExtIntInit->u32ExtIntLevel));
        DDL_ASSERT(IS_EXTINT_CH(u32Ch));
        DDL_ASSERT(IS_INTC_UNLOCK());

        for (u32ExtIntPos = 0UL; u32ExtIntPos < 12UL; u32ExtIntPos++)
        {
            if (0UL != (u32Ch & (1UL << u32ExtIntPos)))
            {
                WRITE_REG32(*(uint32_t *)((uint32_t)(&CM_INTC->EIRQCR0) + 4U*u32ExtIntPos), \
                          (pstcExtIntInit->u32ExtIntFilter         |                        \
                           pstcExtIntInit->u32ExtIntFilterClock    |                        \
                           pstcExtIntInit->u32ExtIntLevel));
            }
        }
    }
    return enRet;
}

/**
 * @brief  Initialize ExtInt. Fill each pstcExtIntInit with default value
 * @param  [in] pstcExtIntInit: Pointer to a pstcExtIntInit structure
 *                              that contains configuration information.
 * @retval Ok: EXTINT structure initialize successful
 *         ErrorInvalidParameter: NULL pointer
 */
en_result_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit)
{
    en_result_t enRet = Ok;

    /* Check if pointer is NULL */
    if (NULL == pstcExtIntInit)
    {
        enRet = ErrorInvalidParameter;
    }
    else
    {
        /* Configure to default value */
        pstcExtIntInit->u32ExtIntFilter      = EXTINT_FILTER_OFF;
        pstcExtIntInit->u32ExtIntFilterClock = EXTINT_FILTER_CLK_DIV1;
        pstcExtIntInit->u32ExtIntLevel       = EXTINT_TRIG_FALLING;
    }
    return enRet;
}

/**
 * @brief  Clear specified External interrupt trigger source
 * @param  [in] u32Ch: External interrupt channel, @ref EXTINT_Channel_Sel for details
 *   @arg  EXTINT_CH00
 *   @arg  EXTINT_CH01
 *   @arg  EXTINT_CH02
 *   @arg  EXTINT_CH03
 *   @arg  EXTINT_CH04
 *   @arg  EXTINT_CH05
 *   @arg  EXTINT_CH06
 *   @arg  EXTINT_CH07
 *   @arg  EXTINT_CH08
 *   @arg  EXTINT_CH09
 *   @arg  EXTINT_CH10
 *   @arg  EXTINT_CH11
 * @retval None
 */
void EXTINT_ClearExtIntStatus(uint32_t u32Ch)
{
    /* Parameter validity checking */
    DDL_ASSERT(IS_EXTINT_CH(u32Ch));
    DDL_ASSERT(IS_INTC_UNLOCK());

    SET_REG16_BIT(CM_INTC->EIRQCLR, u32Ch);
}

/**
 * @brief  Get specified External interrupt trigger source
 * @param  [in] u32Ch: External interrupt channel, @ref EXTINT_Channel_Sel for details
 *   @arg  EXTINT_CH00
 *   @arg  EXTINT_CH01
 *   @arg  EXTINT_CH02
 *   @arg  EXTINT_CH03
 *   @arg  EXTINT_CH04
 *   @arg  EXTINT_CH05
 *   @arg  EXTINT_CH06
 *   @arg  EXTINT_CH07
 *   @arg  EXTINT_CH08
 *   @arg  EXTINT_CH09
 *   @arg  EXTINT_CH10
 *   @arg  EXTINT_CH11
 * @retval Set: Specified channel of external interrupt is triggered
 *         Reset: Specified channel of external interrupt is not triggered
 */
en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32Ch)
{
    /* Parameter validity checking */
    DDL_ASSERT(IS_EXTINT_CH(u32Ch));

    return (0UL != (READ_REG32(CM_INTC->EIRQFR) & u32Ch)) ? Set : Reset;
}

/**
 * @brief  Configure the specified EKEY
 * @param  [in] u8EKey: EKEY channel, @ref INTC_EKEY_Channel for details
 *   @arg  EKEY_CH00
 *   @arg  EKEY_CH01
 *   @arg  EKEY_CH02
 *   @arg  EKEY_CH03
 *   @arg  EKEY_CH04
 *   @arg  EKEY_CH05
 *   @arg  EKEY_CH06
 *   @arg  EKEY_CH07
 * @param  [in] enNewState
 *   @arg  Enable: Enable corresponding EKEY
 *   @arg  Disable: Disable corresponding EKEY
 * @retval None
 */
void INTC_EKeyCmd(uint8_t u8EKey, en_functional_state_t enNewState)
{
    /* Parameter validity checking */
    DDL_ASSERT(IS_INTC_EKEY(u8EKey));
    DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
    DDL_ASSERT(IS_INTC_UNLOCK());

    if (Enable == enNewState)
    {
        SET_REG8_BIT(CM_INTC->EKEYCR, u8EKey);
    }
    else
    {
        CLEAR_REG8_BIT(CM_INTC->EKEYCR, u8EKey);
    }
}

/**
 * @brief  NMI IRQ handler
 * @param  None
 * @retval None
 */
void NMI_Handler(void)
{
    NMI_IrqHandler();
}

/**
 * @brief  Hard Fault IRQ handler
 * @param  None
 * @retval None
 */
void HardFault_Handler(void)
{
    HardFault_IrqHandler();
}

/**
 * @brief  SVCall IRQ handler
 * @param  None
 * @retval None
 */
void SVC_Handler(void)
{
    SVC_IrqHandler();
}

/**
 * @brief  PendSV IRQ handler
 * @param  None
 * @retval None
 */
void PendSV_Handler(void)
{
    PendSV_IrqHandler();
}

/**
 * @brief  SysTick IRQ handler
 * @param  None
 * @retval None
 */
void SysTick_Handler(void)
{
    SysTick_IrqHandler();
}

/**
 * @brief  Interrupt No.000 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ000_Handler(void)
{
    EXTINT00_IrqHandler();
}

/**
 * @brief  Interrupt No.001 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ001_Handler(void)
{
    EXTINT01_IrqHandler();
}

/**
 * @brief  Interrupt No.002 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ002_Handler(void)
{
    EXTINT02_IrqHandler();
}

/**
 * @brief  Interrupt No.003 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ003_Handler(void)
{
    EXTINT03_IrqHandler();
}

/**
 * @brief  Interrupt No.004 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ004_Handler(void)
{
    EXTINT04_IrqHandler();
}

/**
 * @brief  Interrupt No.005 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ005_Handler(void)
{
    EXTINT05_IrqHandler();
}

/**
 * @brief  Interrupt No.006 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ006_Handler(void)
{
    EXTINT06_IrqHandler();
}

/**
 * @brief  Interrupt No.007 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ007_Handler(void)
{
    EXTINT07_IrqHandler();
}

/**
 * @brief  Interrupt No.008 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ008_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT008_IRQn-8U]();
}

/**
 * @brief  Interrupt No.009 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ009_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT009_IRQn-8U]();
}

/**
 * @brief  Interrupt No.010 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ010_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT010_IRQn-8U]();
}


/**
 * @brief  Interrupt No.011 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ011_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT011_IRQn-8U]();
}

/**
 * @brief  Interrupt No.012 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ012_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT012_IRQn-8U]();
}

/**
 * @brief  Interrupt No.013 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ013_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT013_IRQn-8U]();
}

/**
 * @brief  Interrupt No.014 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ014_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT014_IRQn-8U]();
}

/**
 * @brief  Interrupt No.015 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ015_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT015_IRQn-8U]();
}

/**
 * @brief  Interrupt No.016 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ016_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT016_IRQn-8U]();
}

/**
 * @brief  Interrupt No.017 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ017_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT017_IRQn-8U]();
}

/**
 * @brief  Interrupt No.018 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ018_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT018_IRQn-8U]();
}

/**
 * @brief  Interrupt No.019 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ019_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT019_IRQn-8U]();
}

/**
 * @brief  Interrupt No.020 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ020_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT020_IRQn-8U]();
}

/**
 * @brief  Interrupt No.021 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ021_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT021_IRQn-8U]();
}

/**
 * @brief  Interrupt No.022 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ022_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT022_IRQn-8U]();
}

/**
 * @brief  Interrupt No.023 IRQ handler
 * @param  None
 * @retval None
 */
void IRQ023_Handler(void)
{
    m_apfnIrqHandler[(uint32_t)INT023_IRQn-8U]();
}

/**
 * @brief  Interrupt No.024 share IRQ handler
 * @param  None
 * @retval None
 */
void IRQ024_Handler(void)
{
    uint32_t u32Tmp1;
    uint32_t u32Tmp2;
    /* External interrupt 08 */
    u32Tmp1 = bCM_INTC->EIRQFR_b.EIRQF8;
    if ((1UL == bCM_INTC->ISELBR24_b.ISEL1) && (0UL != u32Tmp1))
    {
        EXTINT08_IrqHandler();
    }
    /* DMA Ch.0 transfer complete */
    if (0UL == bCM_DMA->INTMASK1_b.MSKTC0)
    {
        u32Tmp1 = bCM_DMA->INTSTAT1_b.TC0;
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL2) && (0UL != u32Tmp1))
        {
            DMA_TC0_IrqHandler();
        }
    }
    /* DMA Ch.0 block transfer complete */
    if (0UL == bCM_DMA->INTMASK1_b.MSKBTC0)
    {
        u32Tmp1 = bCM_DMA->INTSTAT1_b.BTC0;
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL3) && (0UL != u32Tmp1))
        {
            DMA_BTC0_IrqHandler();
        }
    }
    /* EFM program/erase error */
    if (1UL == bCM_EFM->FITE_b.PEERRITE)
    {
        u32Tmp1 = CM_EFM->FSR & (EFM_FSR_PEWERR | EFM_FSR_PEPRTERR | EFM_FSR_PGMISMTCH);
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL4) && (0UL != u32Tmp1))
        {
            EFM_ProgramEraseError_IrqHandler();
        }
    }
    /* EFM read collision */
    if (1UL == bCM_EFM->FITE_b.COLERRITE)
    {
        u32Tmp1 = bCM_EFM->FSR_b.COLERR;
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL5) && (0UL != u32Tmp1))
        {
            EFM_ColError_IrqHandler();
        }
    }
    /* XTAL stop */
    if (1UL == bCM_CMU->XTALSTDCR_b.XTALSTDIE)
    {
        u32Tmp1 = bCM_CMU->XTALSTDSR_b.XTALSTDF;
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL6) && (0UL != u32Tmp1))
        {
            CLK_XtalStop_IrqHandler();
        }
    }
    /* SWDT underflow or fresh error */
    u32Tmp1 = CM_SWDT->SR & (SWDT_SR_UDF | SWDT_SR_REF);
    if ((1UL == bCM_INTC->ISELBR24_b.ISEL7) &&  (0UL != u32Tmp1))
    {
        SWDT_IrqHandler();
    }
    /* TimerB7 overflow */
    if (1UL == bCM_TMRB_7->BCSTR_b.ITENOVF)
    {
        u32Tmp1 = bCM_TMRB_7->BCSTR_b.OVFF;
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL8) && (0UL != u32Tmp1))
        {
            TMRB_7_Ovf_IrqHandler();
        }
    }
    /* TimerB7 underflow */
    if (1UL == bCM_TMRB_7->BCSTR_b.ITENUDF)
    {
        u32Tmp1 = bCM_TMRB_7->BCSTR_b.UDFF;
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL9) && (0UL != u32Tmp1))
        {
            TMRB_7_Udf_IrqHandler();
        }
    }
    /* TimerB8 compare match */
    if (1UL == bCM_TMRB_8->ICONR_b.ITEN1)
    {
        u32Tmp1 = bCM_TMRB_8->STFLR_b.CMPF1;
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL10) && (1UL== u32Tmp1))
        {
            TMRB_8_Cmp_IrqHandler();
        }
    }
    /* USART5 Rx ORE/FE/PE error */
    if (1UL == bCM_USART5->CR1_b.RIE)
    {
        u32Tmp1 = CM_USART5->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE);
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL11) && (0UL != u32Tmp1))
        {
            USART5_RxError_IrqHandler();
        }
    }
    /* USART1 Rx ORE/FE/PE error */
    if (1UL == bCM_USART1->CR1_b.RIE)
    {
        u32Tmp1 = CM_USART1->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE);
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL12) && (0UL != u32Tmp1))
        {
            USART1_RxError_IrqHandler();
        }
    }
    /* I2c error and event */
    u32Tmp1 = CM_I2C->SR & (I2C_SR_STARTF   | I2C_SR_SLADDR0F       |           \
                            I2C_SR_SLADDR1F | I2C_SR_STOPF          |           \
                            I2C_SR_ARLOF    | I2C_SR_NACKF          |           \
                            I2C_SR_GENCALLF | I2C_SR_SMBDEFAULTF    |           \
                            I2C_SR_SMBHOSTF | I2C_SR_SMBALRTF);

    u32Tmp2 = CM_I2C->CR2& (I2C_CR2_STARTIE  | I2C_CR2_SLADDR0IE    |           \
                            I2C_CR2_SLADDR1IE| I2C_CR2_STOPIE       |           \
                            I2C_CR2_ARLOIE   | I2C_CR2_NACKIE       |           \
                            I2C_CR2_GENCALLIE| I2C_CR2_SMBDEFAULTIE |           \
                            I2C_CR2_SMBHOSTIE| I2C_CR2_SMBALRTIE);
    if ((1UL == bCM_INTC->ISELBR24_b.ISEL13) && (0UL != (u32Tmp1 & u32Tmp2)))
    {
        I2C_EE_IrqHandler();
    }
    /* SPI parity/overflow/underflow/mode error */
    if (1UL == bCM_SPI->CR1_b.EIE)
    {
        u32Tmp1 = CM_SPI->SR & (SPI_SR_UDRERF | SPI_SR_PERF | SPI_SR_MODFERF | SPI_SR_OVRERF);
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL14) && (0UL != u32Tmp1))
        {
            SPI_Error_IrqHandler();
        }
    }
    /* USART4 Rx ORE/FE/PE error */
    if (1UL == bCM_USART4->CR1_b.RIE)
    {
        u32Tmp1 = CM_USART4->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE);
        if ((1UL == bCM_INTC->ISELBR24_b.ISEL15) &&  (0UL != u32Tmp1))
        {
            USART4_RxError_IrqHandler();
        }
    }
}

/**
 * @brief  Interrupt No.025 share IRQ handler
 * @param  None
 * @retval None
 */
void IRQ025_Handler(void)
{
    uint32_t u32Tmp1;
    /* External interrupt 09 */
    u32Tmp1 = bCM_INTC->EIRQFR_b.EIRQF9;
    if ((1UL == bCM_INTC->ISELBR25_b.ISEL1) && (0UL != u32Tmp1))
    {
        EXTINT09_IrqHandler();
    }
    /* DMA Ch.1 transfer complete */
    if (0UL == bCM_DMA->INTMASK1_b.MSKTC1)
    {
        u32Tmp1 = bCM_DMA->INTSTAT1_b.TC1;
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL2) && (0UL != u32Tmp1))
        {
            DMA_TC1_IrqHandler();
        }
    }
    /* DMA Ch.1 block transfer complete */
    if (0UL == bCM_DMA->INTMASK1_b.MSKBTC1)
    {
        u32Tmp1 = bCM_DMA->INTSTAT1_b.BTC1;
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL3) && (0UL != u32Tmp1))
        {
            DMA_BTC1_IrqHandler();
        }
    }
    /* Clock trimming error */
    if (1UL == bCM_CTC->CR1_b.ERRIE)
    {
        u32Tmp1 = CM_CTC->STR & (CTC_STR_TRMOVF | CTC_STR_TRMUDF);
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL4) && (0UL != u32Tmp1))
        {
            CTC_IrqHandler();
        }
    }
    /* TimerB8 overflow */
    if (1UL == bCM_TMRB_8->BCSTR_b.ITENOVF)
    {
        u32Tmp1 = bCM_TMRB_8->BCSTR_b.OVFF;
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL8) && (0UL != u32Tmp1))
        {
            TMRB_8_Ovf_IrqHandler();
        }
    }
    /* TimerB8 underflow */
    if (1UL == bCM_TMRB_8->BCSTR_b.ITENUDF)
    {
        u32Tmp1 = bCM_TMRB_8->BCSTR_b.UDFF;
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL9) && (0UL != u32Tmp1))
        {
            TMRB_8_Udf_IrqHandler();
        }
    }
    /* TimerB7 compare match */
    if (1UL == bCM_TMRB_7->ICONR_b.ITEN1)
    {
        u32Tmp1 = bCM_TMRB_7->STFLR_b.CMPF1;
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL10) && (0UL != u32Tmp1))
        {
            TMRB_7_Cmp_IrqHandler();
        }
    }
    /* USART6 Rx ORE/FE/PE error */
    if (1UL == bCM_USART6->CR1_b.RIE)
    {
        u32Tmp1 = CM_USART6->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE);
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL11) && (0UL != u32Tmp1))
        {
            USART6_RxError_IrqHandler();
        }
    }
    /* USART1 Rx end */
    if (1UL == bCM_USART1->CR1_b.RIE)
    {
        u32Tmp1 = bCM_USART1->SR_b.RXNE;
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL12) && (0UL != u32Tmp1))
        {
            USART1_RxEnd_IrqHandler();
        }
    }
    /* USART4 Rx end */
    if (1UL == bCM_USART4->CR1_b.RIE)
    {
        u32Tmp1 = bCM_USART4->SR_b.RXNE;
        if ((1UL == bCM_INTC->ISELBR25_b.ISEL15) && (0UL != u32Tmp1))
        {
            USART4_RxEnd_IrqHandler();
        }
    }
}

/**
 * @brief  Interrupt No.026 share IRQ handler
 * @param  None
 * @retval None
 */
void IRQ026_Handler(void)
{
    uint32_t u32Tmp1;
    uint32_t u32Tmp2;
    /* DMA request or transfer error */
    u32Tmp1 = CM_DMA->INTSTAT0 & (DMA_INTSTAT0_TRNERR | DMA_INTSTAT0_REQERR);
    u32Tmp2 = (uint32_t)(~(CM_DMA->INTMASK0) & (DMA_INTMASK0_MSKTRNERR | DMA_INTMASK0_MSKREQERR));
    if ((1UL == bCM_INTC->ISELBR26_b.ISEL1) && (0UL != (u32Tmp1 & u32Tmp2)))
    {
        DMA_Error_IrqHandler();
    }
    /* TimerB5 overflow */
    if (1UL == bCM_TMRB_5->BCSTR_b.ITENOVF)
    {
        u32Tmp1 = bCM_TMRB_5->BCSTR_b.OVFF;
        if ((1UL == bCM_INTC->ISELBR26_b.ISEL8) && (0UL != u32Tmp1))
        {
            TMRB_5_Ovf_IrqHandler();
        }
    }
    /* TimerB5 underflow */
    if (1UL == bCM_TMRB_5->BCSTR_b.ITENUDF)
    {
        u32Tmp1 = bCM_TMRB_5->BCSTR_b.UDFF;
        if ((1UL == bCM_INTC->ISELBR26_b.ISEL9) && (0UL != u32Tmp1))
        {
            TMRB_5_Udf_IrqHandler();
        }
    }
    /* TimerB6 compare match */
    if (1UL == bCM_TMRB_6->ICONR_b.ITEN1)
    {
        u32Tmp1 = bCM_TMRB_6->STFLR_b.CMPF1;
        if ((1UL == bCM_INTC->ISELBR26_b.ISEL10) && (0UL != u32Tmp1))
        {
            TMRB_6_Cmp_IrqHandler();
        }
    }
    /* USART5 Rx end */
    if (1UL == bCM_USART5->CR1_b.RIE)
    {
        u32Tmp1 = bCM_USART5->SR_b.RXNE;
        if ((1UL == bCM_INTC->ISELBR26_b.ISEL11) && (0UL != u32Tmp1))
        {
            USART5_RxEnd_IrqHandler();
        }
    }
    /* USART1 Tx buffer empty */
    if (1UL == bCM_USART1->CR1_b.TXEIE)
    {
        u32Tmp1 = bCM_USART1->SR_b.TXE;
        if ((1UL == bCM_INTC->ISELBR26_b.ISEL12) && (0UL != u32Tmp1))
        {
            USART1_TxEmpty_IrqHandler();
        }
    }
    /* USART3 Rx ORE/FE/PE error */
    if (1UL == bCM_USART3->CR1_b.RIE)
    {
        u32Tmp1 = CM_USART3->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE);
        if ((1UL == bCM_INTC->ISELBR26_b.ISEL13) && (0UL != u32Tmp1))
        {
            USART3_RxError_IrqHandler();
        }
    }
}

/**
 * @brief  Interrupt No.027 share IRQ handler
 * @param  None
 * @retval None
 */
void IRQ027_Handler(void)
{
    uint32_t u32Tmp1;
    /* EKEY and other Interrupt source are exclusive */
    if (1UL == bCM_INTC->ISELBR27_b.ISEL1)
    {
        EKEY_IrqHandler();
    }
    else
    {
        /* Timer 0 compare match */
        if (1UL == bCM_TMR0->BCONR_b.INTENA)
        {
            u32Tmp1 = bCM_TMR0->STFLR_b.CMFA;
            if ((1UL == bCM_INTC->ISELBR27_b.ISEL2) && (0UL != u32Tmp1))
            {
                TMR0_CmpA_IrqHandler();
            }
        }
        /* USART6 Rx end */
        if (1UL == bCM_USART6->CR1_b.RIE)
        {
            u32Tmp1 = bCM_USART6->SR_b.RXNE;
            if ((1UL == bCM_INTC->ISELBR27_b.ISEL3) && (0UL != u32Tmp1))
            {
                USART6_RxEnd_IrqHandler();
            }
        }
        /* TimerB6 overflow */
        if (1UL == bCM_TMRB_6->BCSTR_b.ITENOVF)
        {
            u32Tmp1 = bCM_TMRB_6->BCSTR_b.OVFF;
            if ((1UL == bCM_INTC->ISELBR27_b.ISEL8) && (0UL != u32Tmp1))
            {
                TMRB_6_Ovf_IrqHandler();
            }
        }
        /* TimerB6 underflow */
        if (1UL == bCM_TMRB_6->BCSTR_b.ITENUDF)
        {
            u32Tmp1 = bCM_TMRB_6->BCSTR_b.UDFF;
            if ((1UL == bCM_INTC->ISELBR27_b.ISEL9) && (0UL != u32Tmp1))
            {
                TMRB_6_Udf_IrqHandler();
            }
        }
        /* TimerB5 compare match */
        if (1UL == bCM_TMRB_5->ICONR_b.ITEN1)
        {
            u32Tmp1 = bCM_TMRB_5->STFLR_b.CMPF1;
            if ((1UL == bCM_INTC->ISELBR27_b.ISEL10) && (0UL != u32Tmp1))
            {
                TMRB_5_Cmp_IrqHandler();
            }
        }
        /* USART1 Tx end */
        if (1UL == bCM_USART1->CR1_b.TCIE)
        {
            u32Tmp1 = bCM_USART1->SR_b.TC;
            if ((1UL == bCM_INTC->ISELBR27_b.ISEL12) && (0UL != u32Tmp1))
            {
                USART1_TxEnd_IrqHandler();
            }
        }
        /* USART3 Rx end */
        if (1UL == bCM_USART3->CR1_b.RIE)
        {
            u32Tmp1 = bCM_USART3->SR_b.RXNE;
            if ((1UL == bCM_INTC->ISELBR27_b.ISEL13) && (0UL != u32Tmp1))
            {
                USART3_RxEnd_IrqHandler();
            }
        }
        /* SPI Rx end */
        if (1UL == bCM_SPI->CR1_b.RXIE)
        {
            u32Tmp1 = bCM_SPI->SR_b.RDFF;
            if ((1UL == bCM_INTC->ISELBR27_b.ISEL14) && (0UL != u32Tmp1))
            {
                SPI_RxEnd_IrqHandler();
            }
        }
    }
}

/**
 * @brief  Interrupt No.028 share IRQ handler
 * @param  None
 * @retval None
 */
void IRQ028_Handler(void)
{
    uint32_t u32Tmp1;
    /* USART5 Tx buffer empty */
    if (1UL == bCM_USART5->CR1_b.TXEIE)
    {
        u32Tmp1 = bCM_USART5->SR_b.TXE;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL7) && (0UL != u32Tmp1))
        {
            USART5_TxEmpty_IrqHandler();
        }
    }
    /* TimerB3 overflow */
    if (1UL == bCM_TMRB_3->BCSTR_b.ITENOVF)
    {
        u32Tmp1 = bCM_TMRB_3->BCSTR_b.OVFF;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL8) && (0UL != u32Tmp1))
        {
            TMRB_3_Ovf_IrqHandler();
        }
    }
    /* TimerB3 underflow */
    if (1UL == bCM_TMRB_3->BCSTR_b.ITENUDF)
    {
        u32Tmp1 = bCM_TMRB_3->BCSTR_b.UDFF;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL9) && (0UL != u32Tmp1))
        {
            TMRB_3_Udf_IrqHandler();
        }
    }
    /* TimerB4 compare match */
    if (1UL == bCM_TMRB_4->ICONR_b.ITEN1)
    {
        u32Tmp1 = bCM_TMRB_4->STFLR_b.CMPF1;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL10) && (0UL != u32Tmp1))
        {
            TMRB_4_Cmp_IrqHandler();
        }
    }
    /* ADC seq.A convert complete */
    if (1UL == bCM_ADC->ICR_b.EOCAIEN)
    {
        u32Tmp1 = bCM_ADC->ISR_b.EOCAF;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL11) && (0UL != u32Tmp1))
        {
            ADC_SeqA_IrqHandler();
        }
    }
    /* USART2 Rx ORE/FE/PE error */
    if (1UL == bCM_USART2->CR1_b.RIE)
    {
        u32Tmp1 = CM_USART2->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE);
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL12) && (0UL != u32Tmp1))
        {
            USART2_RxError_IrqHandler();
        }
    }
    /* USART3 Tx buffer empty */
    if (1UL == bCM_USART3->CR1_b.TXEIE)
    {
        u32Tmp1 = bCM_USART3->SR_b.TXE;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL13) && (0UL != u32Tmp1))
        {
            USART3_TxEmpty_IrqHandler();
        }
    }
    /* I2c Tx end */
    if (1UL == bCM_I2C->CR2_b.TENDIE)
    {
        u32Tmp1 = bCM_I2C->SR_b.TENDF;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL14) && (0UL != u32Tmp1))
        {
            I2C_TxEnd_IrqHandler();
        }
    }
    /* SPI bus idle */
    if (1UL == bCM_SPI->CR1_b.IDIE)
    {
        u32Tmp1 = bCM_SPI->SR_b.IDLNF;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL15) && (0UL == u32Tmp1))
        {
            SPI_Idle_IrqHandler();
        }
    }
}

/**
 * @brief  Interrupt No.029 share IRQ handler
 * @param  None
 * @retval None
 */
void IRQ029_Handler(void)
{
    uint32_t u32Tmp1;
    /* External interrupt 10 */
    u32Tmp1 = bCM_INTC->EIRQFR_b.EIRQF10;
    if ((1UL == bCM_INTC->ISELBR29_b.ISEL5) && (0UL != u32Tmp1))
    {
        EXTINT10_IrqHandler();
    }
    /* USART6 Tx buffer empty */
    if (1UL == bCM_USART6->CR1_b.TXEIE)
    {
        u32Tmp1 = bCM_USART6->SR_b.TXE;
        if ((1UL == bCM_INTC->ISELBR29_b.ISEL7) && (0UL != u32Tmp1))
        {
            USART6_TxEmpty_IrqHandler();
        }
    }
    /* TimerB4 overflow */
    if (1UL == bCM_TMRB_4->BCSTR_b.ITENOVF)
    {
        u32Tmp1 = bCM_TMRB_4->BCSTR_b.OVFF;
        if ((1UL == bCM_INTC->ISELBR29_b.ISEL8) && (0UL != u32Tmp1))
        {
            TMRB_4_Ovf_IrqHandler();
        }
    }
    /* TimerB4 underflow */
    if (1UL == bCM_TMRB_4->BCSTR_b.ITENUDF)
    {
        u32Tmp1 = bCM_TMRB_4->BCSTR_b.UDFF;
        if ((1UL == bCM_INTC->ISELBR29_b.ISEL9) && (0UL != u32Tmp1))
        {
            TMRB_4_Udf_IrqHandler();
        }
    }
    /* TimerB3 compare match */
    if (1UL == bCM_TMRB_3->ICONR_b.ITEN1)
    {
        u32Tmp1 = bCM_TMRB_3->STFLR_b.CMPF1;
        if ((1UL == bCM_INTC->ISELBR29_b.ISEL10) && (0UL != u32Tmp1))
        {
            TMRB_3_Cmp_IrqHandler();
        }
    }
    /* ADC seq.B convert complete */
    if (1UL == bCM_ADC->ICR_b.EOCBIEN)
    {
        u32Tmp1 = bCM_ADC->ISR_b.EOCBF;
        if ((1UL == bCM_INTC->ISELBR29_b.ISEL11) && (0UL != u32Tmp1))
        {
            ADC_SeqB_IrqHandler();
        }
    }
    /* USART2 Rx end */
    if (1UL == bCM_USART2->CR1_b.RIE)
    {
        u32Tmp1 = bCM_USART2->SR_b.RXNE;
        if ((1UL == bCM_INTC->ISELBR29_b.ISEL12) && (0UL != u32Tmp1))
        {
            USART2_RxEnd_IrqHandler();
        }
    }
    /* USART3 Tx end */
    if (1UL == bCM_USART3->CR1_b.TCIE)
    {
        u32Tmp1 = bCM_USART3->SR_b.TC;
        if ((1UL == bCM_INTC->ISELBR29_b.ISEL13) && (0UL != u32Tmp1))
        {
            USART3_TxEnd_IrqHandler();
        }
    }
    /* I2c Rx end */
    if (1UL == bCM_I2C->CR2_b.RFULLIE)
    {
        u32Tmp1 = bCM_I2C->SR_b.RFULLF;
        if ((1UL == bCM_INTC->ISELBR29_b.ISEL14) && (0UL != u32Tmp1))
        {
            I2C_RxEnd_IrqHandler();
        }
    }
}

/**
 * @brief  Interrupt No.030 share IRQ handler
 * @param  None
 * @retval None
 */
void IRQ030_Handler(void)
{
    uint32_t u32Tmp1;
    /* External interrupt 11 */
    u32Tmp1 = bCM_INTC->EIRQFR_b.EIRQF11;
    if ((1UL == bCM_INTC->ISELBR30_b.ISEL5) && (0UL != u32Tmp1))
    {
        EXTINT11_IrqHandler();
    }
    /* USART1 Tx end */
    if (1UL == bCM_USART5->CR1_b.TCIE)
    {
        u32Tmp1 = bCM_USART5->SR_b.TC;
        if ((1UL == bCM_INTC->ISELBR30_b.ISEL7) && (0UL != u32Tmp1))
        {
            USART5_TxEnd_IrqHandler();
        }
    }
    /* TimerB1 overflow */
    if (1UL == bCM_TMRB_1->BCSTR_b.ITENOVF)
    {
        u32Tmp1 = bCM_TMRB_1->BCSTR_b.OVFF;
        if ((1UL == bCM_INTC->ISELBR30_b.ISEL8) && (0UL != u32Tmp1))
        {
            TMRB_1_Ovf_IrqHandler();
        }
    }
    /* TimerB1 underflow */
    if (1UL ==bCM_TMRB_1->BCSTR_b.ITENUDF)
    {
        u32Tmp1 = bCM_TMRB_1->BCSTR_b.UDFF;
        if ((1UL == bCM_INTC->ISELBR30_b.ISEL9) && (0UL != u32Tmp1))
        {
            TMRB_1_Udf_IrqHandler();
        }
    }
    /* TimerB2 compare match */
    if (1UL == bCM_TMRB_2->ICONR_b.ITEN1)
    {
        u32Tmp1 = bCM_TMRB_2->STFLR_b.CMPF1;
        if ((1UL == bCM_INTC->ISELBR30_b.ISEL10) && (0UL != u32Tmp1))
        {
            TMRB_2_Cmp_IrqHandler();
        }
    }
    /* ADC convert result in range of window 0 setting */
    if (1UL == bCM_ADC->AWDCR_b.AWD0IEN)
    {
        u32Tmp1 = bCM_ADC->AWDSR_b.AWD0F;
        if ((1UL == bCM_INTC->ISELBR30_b.ISEL11) && (0UL != u32Tmp1))
        {
            ADC_Cmp0_IrqHandler();
        }
    }
    /* USART2 Tx buffer empty */
    if (1UL == bCM_USART2->CR1_b.TXEIE)
    {
        u32Tmp1 = bCM_USART2->SR_b.TXE;
        if ((1UL == bCM_INTC->ISELBR30_b.ISEL12) && (0UL != u32Tmp1))
        {
            USART2_TxEmpty_IrqHandler();
        }
    }
    /* I2c Tx buffer empty */
    if (1UL == bCM_I2C->CR2_b.TEMPTYIE)
    {
        u32Tmp1 = bCM_I2C->SR_b.TEMPTYF;
        if ((1UL == bCM_INTC->ISELBR28_b.ISEL14) && (0UL != u32Tmp1))
        {
            I2C_TxEmpty_IrqHandler();
        }
    }
    /* USART4 Tx buffer empty */
    if (1UL == bCM_USART4->CR1_b.TXEIE)
    {
        u32Tmp1 = bCM_USART4->SR_b.TXE;
        if ((1UL == bCM_INTC->ISELBR30_b.ISEL15) && (0UL != u32Tmp1))
        {
            USART4_TxEmpty_IrqHandler();
        }
    }
}

/**
 * @brief  Interrupt No.031 share IRQ handler
 * @param  None
 * @retval None
 */
void IRQ031_Handler(void)
{
    uint32_t u32Tmp1;
    uint32_t u32Tmp2;
    /* LVD detected */
    if (0UL == bCM_EFM->PWC_LVDICGCR_b.LVDDIS)
    {
        u32Tmp1 = bCM_PWC->LVDCSR_b.DETF;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL2) && (0UL != u32Tmp1))
        {
            PWC_LVD_IrqHandler();
        }
    }
    /* USART6 Tx end */
    if (1UL == bCM_USART6->CR1_b.TCIE)
    {
        u32Tmp1 = bCM_USART6->SR_b.TC;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL3) && (0UL != u32Tmp1))
        {
            USART6_TxEnd_IrqHandler();
        }
    }
    /* EFM operate end */
    if (1UL == bCM_EFM->FITE_b.OPTENDITE)
    {
        u32Tmp1 = bCM_EFM->FSR_b.OPTEND;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL4) && (0UL != u32Tmp1))
        {
            EFM_OpEnd_IrqHandler();
        }
    }
    /* RTC alarm */
    if (1UL == bCM_RTC->CR2_b.ALMIE)
    {
        u32Tmp1 = bCM_RTC->CR2_b.ALMF;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL5) && (0UL != u32Tmp1))
        {
            RTC_Alarm_IrqHandler();
        }
    }
    /* RTC period */
    if (1UL == bCM_RTC->CR2_b.PRDIE)
    {
        u32Tmp1 = bCM_RTC->CR2_b.PRDF;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL6) && (0UL != u32Tmp1))
        {
            RTC_Period_IrqHandler();
        }
    }
    /* TimerB2 overflow */
    if (1UL == bCM_TMRB_2->BCSTR_b.ITENOVF)
    {
        u32Tmp1 = bCM_TMRB_2->BCSTR_b.OVFF;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL8) && (0UL != u32Tmp1))
        {
            TMRB_2_Ovf_IrqHandler();
        }
    }
    /* TimerB2 underflow */
    if (1UL == bCM_TMRB_2->BCSTR_b.ITENUDF)
    {
        u32Tmp1 = bCM_TMRB_2->BCSTR_b.UDFF;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL9) && (0UL != u32Tmp1))
        {
            TMRB_2_Udf_IrqHandler();
        }
    }
    /* TimerB1 compare match */
    if (1UL == bCM_TMRB_1->ICONR_b.ITEN1)
    {
        u32Tmp1 = bCM_TMRB_1->STFLR_b.CMPF1;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL10) && (0UL != u32Tmp1))
        {
            TMRB_1_Cmp_IrqHandler();
        }
    }
    if (1UL == bCM_ADC->AWDCR_b.AWD1IEN)
    {
        /* ADC convert result in range of window 1 if independence use */
        u32Tmp1 = bCM_ADC->AWDSR_b.AWD1F;
        u32Tmp2 = (uint32_t)CM_ADC->AWDCR & (uint32_t)ADC_AWDCR_AWDCM;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL11) && (0UL != u32Tmp1) && (0UL == u32Tmp2))
        {
            ADC_Cmp1_IrqHandler();
        }
        /* ADC convert result combination use of window 0 & 1 */
        u32Tmp1 = bCM_ADC->AWDSR_b.AWDCMF;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL11) && (0UL != u32Tmp1) && (0UL != u32Tmp2))
        {
            ADC_Cmp1_IrqHandler();
        }
    }
    /* USART2 Tx end */
    if (1UL == bCM_USART2->CR1_b.TCIE)
    {
        u32Tmp1 = bCM_USART2->SR_b.TC;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL12) && (0UL != u32Tmp1))
        {
            USART2_TxEnd_IrqHandler();
        }
    }
    /* SPI Tx buffer empty */
    if (1UL == bCM_SPI->CR1_b.TXIE)
    {
        u32Tmp1 = bCM_SPI->SR_b.TDEF;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL13) && (0UL != u32Tmp1))
        {
            SPI_TxEmpty_IrqHandler();
        }
    }
    /* USART4 Tx end */
    if (1UL == bCM_USART4->CR1_b.TCIE)
    {
        u32Tmp1 = bCM_USART4->SR_b.TC;
        if ((1UL == bCM_INTC->ISELBR31_b.ISEL15) && (0UL != u32Tmp1))
        {
            USART4_TxEnd_IrqHandler();
        }
    }
}
/**
 * @}
 */

/**
 * @defgroup INTC_Weakdef_Prototypes INTC weak function prototypes
 * @{
 */
__WEAKDEF void HardFault_IrqHandler(void)
{

}

__WEAKDEF void SVC_IrqHandler(void)
{

}

__WEAKDEF void PendSV_IrqHandler(void)
{

}

__WEAKDEF void SysTick_IrqHandler(void)
{

}

__WEAKDEF void EXTINT00_IrqHandler(void)
{

}

__WEAKDEF void EXTINT01_IrqHandler(void)
{

}

__WEAKDEF void EXTINT02_IrqHandler(void)
{

}

#if (BSP_OFF == BSP_INT_KEY_ENABLE)
__WEAKDEF void EXTINT03_IrqHandler(void)
{

}

__WEAKDEF void EXTINT04_IrqHandler(void)
{

}

__WEAKDEF void EXTINT05_IrqHandler(void)
{

}

__WEAKDEF void EXTINT06_IrqHandler(void)
{

}
#endif
__WEAKDEF void EXTINT07_IrqHandler(void)
{

}

__WEAKDEF void EXTINT08_IrqHandler(void)
{

}

__WEAKDEF void EXTINT09_IrqHandler(void)
{

}

__WEAKDEF void EXTINT10_IrqHandler(void)
{

}

__WEAKDEF void EXTINT11_IrqHandler(void)
{

}

__WEAKDEF void DMA_TC0_IrqHandler(void)
{

}

__WEAKDEF void DMA_BTC0_IrqHandler(void)
{

}

__WEAKDEF void DMA_TC1_IrqHandler(void)
{

}

__WEAKDEF void DMA_BTC1_IrqHandler(void)
{

}

__WEAKDEF void DMA_Error_IrqHandler(void)
{

}

__WEAKDEF void EFM_ProgramEraseError_IrqHandler(void)
{

}

__WEAKDEF void EFM_ColError_IrqHandler(void)
{

}

__WEAKDEF void EFM_OpEnd_IrqHandler(void)
{

}

__WEAKDEF void CLK_XtalStop_IrqHandler(void)
{

}

__WEAKDEF void SWDT_IrqHandler(void)
{

}

__WEAKDEF void TMRB_1_Ovf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_1_Udf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_1_Cmp_IrqHandler(void)
{

}

__WEAKDEF void TMRB_2_Ovf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_2_Udf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_2_Cmp_IrqHandler(void)
{

}

__WEAKDEF void TMRB_3_Ovf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_3_Udf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_3_Cmp_IrqHandler(void)
{

}

__WEAKDEF void TMRB_4_Ovf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_4_Udf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_4_Cmp_IrqHandler(void)
{

}

__WEAKDEF void TMRB_5_Ovf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_5_Udf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_5_Cmp_IrqHandler(void)
{

}

__WEAKDEF void TMRB_6_Ovf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_6_Udf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_6_Cmp_IrqHandler(void)
{

}

__WEAKDEF void TMRB_7_Ovf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_7_Udf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_7_Cmp_IrqHandler(void)
{

}

__WEAKDEF void TMRB_8_Ovf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_8_Udf_IrqHandler(void)
{

}

__WEAKDEF void TMRB_8_Cmp_IrqHandler(void)
{

}

__WEAKDEF void USART1_RxError_IrqHandler(void)
{

}

__WEAKDEF void USART1_RxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART1_TxEmpty_IrqHandler(void)
{

}

__WEAKDEF void USART1_TxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART2_RxError_IrqHandler(void)
{

}

__WEAKDEF void USART2_RxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART2_TxEmpty_IrqHandler(void)
{

}

__WEAKDEF void USART2_TxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART3_RxError_IrqHandler(void)
{

}

__WEAKDEF void USART3_RxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART3_TxEmpty_IrqHandler(void)
{

}

__WEAKDEF void USART3_TxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART4_RxError_IrqHandler(void)
{

}

__WEAKDEF void USART4_RxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART4_TxEmpty_IrqHandler(void)
{

}

__WEAKDEF void USART4_TxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART5_RxError_IrqHandler(void)
{

}

__WEAKDEF void USART5_RxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART5_TxEmpty_IrqHandler(void)
{

}

__WEAKDEF void USART5_TxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART6_RxError_IrqHandler(void)
{

}

__WEAKDEF void USART6_RxEnd_IrqHandler(void)
{

}

__WEAKDEF void USART6_TxEmpty_IrqHandler(void)
{

}

__WEAKDEF void USART6_TxEnd_IrqHandler(void)
{

}

__WEAKDEF void I2C_RxEnd_IrqHandler(void)
{

}

__WEAKDEF void I2C_TxEmpty_IrqHandler(void)
{

}

__WEAKDEF void I2C_TxEnd_IrqHandler(void)
{

}

__WEAKDEF void I2C_EE_IrqHandler(void)
{

}

__WEAKDEF void SPI_RxEnd_IrqHandler(void)
{

}

__WEAKDEF void SPI_TxEmpty_IrqHandler(void)
{

}

__WEAKDEF void SPI_Idle_IrqHandler(void)
{

}

__WEAKDEF void SPI_Error_IrqHandler(void)
{

}

__WEAKDEF void CTC_IrqHandler(void)
{

}

__WEAKDEF void EKEY_IrqHandler(void)
{

}

__WEAKDEF void TMR0_CmpA_IrqHandler(void)
{

}

__WEAKDEF void ADC_SeqA_IrqHandler(void)
{

}

__WEAKDEF void ADC_SeqB_IrqHandler(void)
{

}

__WEAKDEF void ADC_Cmp0_IrqHandler(void)
{

}

__WEAKDEF void ADC_Cmp1_IrqHandler(void)
{

}

__WEAKDEF void PWC_LVD_IrqHandler(void)
{

}

__WEAKDEF void RTC_Alarm_IrqHandler(void)
{

}

__WEAKDEF void RTC_Period_IrqHandler(void)
{

}

/**
 * @}
 */

#endif /* DDL_INTERRUPTS_ENABLE */

/**
 * @}
 */

/**
* @}
*/

/******************************************************************************
 * EOF (not truncated)
 *****************************************************************************/
